1. Field of the Invention
The present invention relates to package structures and fabricating methods thereof, and more particularly, to a package structure having embedded electronic components and a method of fabricating the same.
2. Description of Related Art
With the advancement in semiconductor packaging technology, various types of packages of the semiconductor device have been developed. A chip scale package (CSP) having the package size as small as or slightly larger than the chip size, is developed in order for meeting the demand of miniaturization.
Referring to FIGS. 1A-1F, a method of fabricating a conventional semiconductor package 1 is shown.
As shown in FIG. 1A, a first carrier 10a having a first adhesive layer 100a is provided, and at least one semiconductor element 11 is disposed on the first adhesive layer 100a, then an encapsulating layer 12 is formed to encapsulate the semiconductor element 11. The semiconductor element 11 has an active surface 11a bonded with the first adhesive layer 100a and an opposing none-active surface 11b having a plurality of electrode pads 110 thereon.
As shown in FIG. 1B, a polishing method is employed to remove a portion of the encapsulating layer 12, allowing the none-active surface 11b of the semiconductor element 11 to be exposed from the second surface 12b of the encapsulating layer 12. Subsequently, the first carrier 10a and the first adhesive layer 100a are removed, and a second carrier 10b having a second adhesive layer 100b is attached on the second surface 12b of the encapsulating layer 12.
As shown in FIG. 1C, a first redistribution layer (RDL) 13 is formed on the first surface 12a of the encapsulating layer 12 and the active surface 11a of the semiconductor element 11, and the first redistribution layer 13 is electrically connected with the electrode pads 110 of the semiconductor element 11.
As shown in FIG. 1D, a third carrier 10c having a third adhesive layer 100c is disposed on the first redistribution layer 13, followed by removing the second carrier 10b and the second adhesive layer 100b. After that, a plurality of vias 121 penetrating the encapsulating layer 12 are formed by laser to expose the first redistribution layer 13.
As shown in FIG. 1E, a second redistribution layer 14 is formed on the second surface 12b of the encapsulating layer 12 and in the vias 121, and is electrically connected with the first redistribution layer 13.
As shown in FIG. 1F, the third adhesive layer 100c and the third carrier 10c are removed, followed by performing a singulation process to form a plurality of conductive elements 15 such as solder balls on the first redistribution layer 13, such that the conductive elements 15 electrically connect the first redistribution layer 13 with the second redistribution layer 14.
However, according to the method of fabricating the semiconductor package 1, the vias 121 formed by laser is not only slow (especially when the number of vias is large) but also time consuming, and the residuals (such as the remaining materials of the encapsulating layer 12) left during the process of forming the vias 121 may easily accumulate at the bottom of the vias 121. Therefore, a cleaning process must be performed to clean the interior of the vias 121 before the conductive materials could be filled in the vias 121 to form the second redistribution layer 14, thereby overcomplicating the steps involved in fabrication.
Second, laser drilling to form openings may cause unevenness of the walls of the vias 121, leading to poor attachment of the conductive materials to the walls of the vias 121, causing peeling, and ultimately resulting in poor reliability for the semiconductor package 1.
Further, the laser drilling process is performed from the second surface 12b of the encapsulating layer 12, but since the encapsulating layer 12 is opaque, the laser equipment could not detect the first redistribution layer 13 under the encapsulating layer 12, and thus requires a specialized process and equipment for alignment, thereby further increasing the complexity and cost in fabrication.
Besides, the laser beam utilized in the laser drilling process would result in a problem of heat affect zone; that is, when the vias 121 are at proximity of the semiconductor element 11, the high temperature heat would damage the semiconductor element 11, and thus the vias 121 must be kept with a certain distance from the semiconductor element 11. As such, the semiconductor package 1 could not be further miniaturized, and is difficult to meet the low-profile requirement.
Meanwhile, the number of steps (at least 3) increases for bonding and removing the carrier (i.e. from the first to the third carrier 10a-10c) during the fabricating process of the semiconductor package 1, thereby overcomplicating the fabricating process, which is time consuming and the fabricating cost is also increased due to more materials required for both the carriers and the adhesive layers.
Thus, there is an urgent need for solving the problems of the prior art.